The use of IO interface circuits, such as, for example, IO buffers, is well-known. In advanced complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) process technology, there has been a push toward lower voltage IO buffers. In a 40 nanometer (nm) IC fabrication process, for example, 1.8-volt transistors are being readily adopted. However, despite the push to utilize lower voltage transistors, there is still a need for high voltage tolerance in certain IO applications that may require interfacing with higher voltages (e.g., 5 volts). One such application is a light emitting diode (LED) driver circuit.
Conventional high voltage tolerant IO interface circuits typically employ stacked metal-oxide-semiconductor (MOS) devices. An example of this configuration is described in U.S. Pat. No. 6,388,475 to Clark et al. While this circuit configuration may help alleviate overvoltage stress on individual devices by distributing the voltage across two or more devices, some high voltage tolerant failsafe specifications require that the circuit tolerate a prescribed voltage even when power to the circuit is removed. This creates a problem for the stacked MOS device approach. Additionally, utilizing stacked MOS devices requires more area in the IC compared to a non-stacked device arrangement and is therefore undesirable.
Another known approach to forming a high voltage tolerant output stage is to employ thick oxide MOS devices. One disadvantage of this approach, however, is that it requires additional IC fabrication steps which increase overall cost.
Accordingly, there exists a need for a high voltage tolerant IO interface circuit which does not suffer from one or more of the above-described problems associated with conventional IO interface circuitry.